Home ›
Entities
› academia
› 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
Research article (2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020) · cited 138× · AI/ML
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
Summary
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models is a scholarly article[1].
Key Facts
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models's instance of is recorded as scholarly article[2].
References
Programmatic citations — every numbered marker resolves to a verifiable graph row below.
Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. Retrieved May 24, 2026, from https://4ort.xyz/entity/33-1-a-74-tmacs-w-cmos-rram-neurosynaptic-core-with-dynamically-reconfigurable-dataflow-and-in-situ-transposable-weights
MLA“33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/33-1-a-74-tmacs-w-cmos-rram-neurosynaptic-core-with-dynamically-reconfigurable-dataflow-and-in-situ-transposable-weights.
BibTeX@misc{4ortxyz_33-1-a-74-tmacs-w-cmos-rram-neurosynaptic-core-with-dynamically-reconfigurable-dataflow-and-in-situ-transposable-weights_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models}}, year = {2026}, url = {https://4ort.xyz/entity/33-1-a-74-tmacs-w-cmos-rram-neurosynaptic-core-with-dynamically-reconfigurable-dataflow-and-in-situ-transposable-weights}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models — https://4ort.xyz/entity/33-1-a-74-tmacs-w-cmos-rram-neurosynaptic-core-with-dynamically-reconfigurable-dataflow-and-in-situ-transposable-weights (retrieved 2026-05-24)
