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32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels
Research article (2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021) · cited 58× · AI/ML
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels
Summary
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels is a scholarly article[1].
Key Facts
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels's instance of is recorded as scholarly article[2].
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APA4ort.xyz Knowledge Graph. (2026). 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. Retrieved May 24, 2026, from https://4ort.xyz/entity/32-2-a-14nm-analog-sampling-fractional-n-pll-with-a-digital-to-time-converter-range-reduction-technique-achieving-80fs-i
MLA“32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/32-2-a-14nm-analog-sampling-fractional-n-pll-with-a-digital-to-time-converter-range-reduction-technique-achieving-80fs-i.
BibTeX@misc{4ortxyz_32-2-a-14nm-analog-sampling-fractional-n-pll-with-a-digital-to-time-converter-range-reduction-technique-achieving-80fs-i_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels}}, year = {2026}, url = {https://4ort.xyz/entity/32-2-a-14nm-analog-sampling-fractional-n-pll-with-a-digital-to-time-converter-range-reduction-technique-achieving-80fs-i}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels — https://4ort.xyz/entity/32-2-a-14nm-analog-sampling-fractional-n-pll-with-a-digital-to-time-converter-range-reduction-technique-achieving-80fs-i (retrieved 2026-05-24)
