19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput

Research article (2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019) · cited 17× · AI/ML
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19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput

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19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput is a scholarly article[1].

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APA 4ort.xyz Knowledge Graph. (2026). 19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. Retrieved May 24, 2026, from https://4ort.xyz/entity/19-7-a-scalable-pipelined-time-domain-dtw-engine-for-time-series-classification-using-multibit-time-flip-flops-with-140g
MLA “19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/19-7-a-scalable-pipelined-time-domain-dtw-engine-for-time-series-classification-using-multibit-time-flip-flops-with-140g.
BibTeX @misc{4ortxyz_19-7-a-scalable-pipelined-time-domain-dtw-engine-for-time-series-classification-using-multibit-time-flip-flops-with-140g_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput}}, year = {2026}, url = {https://4ort.xyz/entity/19-7-a-scalable-pipelined-time-domain-dtw-engine-for-time-series-classification-using-multibit-time-flip-flops-with-140g}, note = {Accessed: 2026-05-24}}
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