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17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
Research article (2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023) · cited 13× · AI/ML
17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
Summary
17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input is a scholarly article[1].
Key Facts
17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input's instance of is recorded as scholarly article[2].
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APA4ort.xyz Knowledge Graph. (2026). 17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. Retrieved May 24, 2026, from https://4ort.xyz/entity/17-1-a-2x-lnterleaved-9b-2-8g8s-s-5b-cycle-sar-adc-with-linearized-configurable-v2t-buffer-achieving-gt-50db-sndr-at-3gh
MLA“17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/17-1-a-2x-lnterleaved-9b-2-8g8s-s-5b-cycle-sar-adc-with-linearized-configurable-v2t-buffer-achieving-gt-50db-sndr-at-3gh.
BibTeX@misc{4ortxyz_17-1-a-2x-lnterleaved-9b-2-8g8s-s-5b-cycle-sar-adc-with-linearized-configurable-v2t-buffer-achieving-gt-50db-sndr-at-3gh_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input}}, year = {2026}, url = {https://4ort.xyz/entity/17-1-a-2x-lnterleaved-9b-2-8g8s-s-5b-cycle-sar-adc-with-linearized-configurable-v2t-buffer-achieving-gt-50db-sndr-at-3gh}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input — https://4ort.xyz/entity/17-1-a-2x-lnterleaved-9b-2-8g8s-s-5b-cycle-sar-adc-with-linearized-configurable-v2t-buffer-achieving-gt-50db-sndr-at-3gh (retrieved 2026-05-24)
