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14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
Research article (2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019) · cited 38× · AI/ML
14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
Summary
14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS is a scholarly article[1].
Key Facts
14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS's instance of is recorded as scholarly article[2].
References
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APA4ort.xyz Knowledge Graph. (2026). 14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. Retrieved May 24, 2026, from https://4ort.xyz/entity/14-5-a-0-6-to-1-1v-computationally-regulated-digital-ldo-with-2-79-cycle-mean-settling-time-and-autonomous-runtime-gain-
MLA“14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/14-5-a-0-6-to-1-1v-computationally-regulated-digital-ldo-with-2-79-cycle-mean-settling-time-and-autonomous-runtime-gain-.
BibTeX@misc{4ortxyz_14-5-a-0-6-to-1-1v-computationally-regulated-digital-ldo-with-2-79-cycle-mean-settling-time-and-autonomous-runtime-gain-_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS}}, year = {2026}, url = {https://4ort.xyz/entity/14-5-a-0-6-to-1-1v-computationally-regulated-digital-ldo-with-2-79-cycle-mean-settling-time-and-autonomous-runtime-gain-}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS — https://4ort.xyz/entity/14-5-a-0-6-to-1-1v-computationally-regulated-digital-ldo-with-2-79-cycle-mean-settling-time-and-autonomous-runtime-gain- (retrieved 2026-05-24)
