14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS

Research article (2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015) · cited 11× · AI/ML
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14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS

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14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS is a scholarly article[1].

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  • 14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS's instance of is recorded as scholarly article[2].

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APA 4ort.xyz Knowledge Graph. (2026). 14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. Retrieved May 24, 2026, from https://4ort.xyz/entity/14-4-a-5ghz-amp-x2212-95dbc-reference-spur-9-5mw-digital-fractional-n-pll-using-reference-multiplied-time-to-digital-con
MLA “14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/14-4-a-5ghz-amp-x2212-95dbc-reference-spur-9-5mw-digital-fractional-n-pll-using-reference-multiplied-time-to-digital-con.
BibTeX @misc{4ortxyz_14-4-a-5ghz-amp-x2212-95dbc-reference-spur-9-5mw-digital-fractional-n-pll-using-reference-multiplied-time-to-digital-con_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS}}, year = {2026}, url = {https://4ort.xyz/entity/14-4-a-5ghz-amp-x2212-95dbc-reference-spur-9-5mw-digital-fractional-n-pll-using-reference-multiplied-time-to-digital-con}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS — https://4ort.xyz/entity/14-4-a-5ghz-amp-x2212-95dbc-reference-spur-9-5mw-digital-fractional-n-pll-using-reference-multiplied-time-to-digital-con (retrieved 2026-05-24)

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