14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS
Research article (2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015) · cited 11× · AI/ML
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14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS
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14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS is a scholarly article[1].
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- 14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS's instance of is recorded as scholarly article[2].