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11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

Research article (2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024) · cited 13× · AI/ML
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11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

Summary

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint is a scholarly article[1].

Key Facts

  • 11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint's instance of is recorded as scholarly article[2].

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Direct Wikidata claims

  1. [2] ↑ . wikidata.org.

Class ancestry

  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). 11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at &lt;2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. Retrieved May 24, 2026, from https://4ort.xyz/entity/11-2-a-3d-integrated-prototype-system-on-chip-for-augmented-reality-applications-using-face-to-face-wafer-bonded-7nm-log
MLA “11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at &lt;2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/11-2-a-3d-integrated-prototype-system-on-chip-for-augmented-reality-applications-using-face-to-face-wafer-bonded-7nm-log.
BibTeX @misc{4ortxyz_11-2-a-3d-integrated-prototype-system-on-chip-for-augmented-reality-applications-using-face-to-face-wafer-bonded-7nm-log_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at &lt;2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint}}, year = {2026}, url = {https://4ort.xyz/entity/11-2-a-3d-integrated-prototype-system-on-chip-for-augmented-reality-applications-using-face-to-face-wafer-bonded-7nm-log}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at &lt;2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint — https://4ort.xyz/entity/11-2-a-3d-integrated-prototype-system-on-chip-for-augmented-reality-applications-using-face-to-face-wafer-bonded-7nm-log (retrieved 2026-05-24)

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