# x86 debug register

> 6 x86 registers used by a processor for program debugging: DR0…DR7 (DR4 and DR5 as obsolete synonyms for DR6 and DR7); accessed by variants of the MOV instruction that can only be executed at privilege level zero

**Wikidata**: [Q8041663](https://www.wikidata.org/wiki/Q8041663)  
**Wikipedia**: [English](https://en.wikipedia.org/wiki/X86_debug_register)  
**Source**: https://4ort.xyz/entity/x86-debug-register

## Summary
The x86 debug register is a set of six processor registers within the x86 architecture specifically designed to support hardware program debugging. These registers, labeled DR0 through DR7, are utilized to monitor and control processor operations. Access to these registers is restricted, requiring variants of the MOV instruction executed at privilege level zero.

## Key Facts
- **Classification:** The x86 debug register is a subclass of the processor register.
- **Quantity:** There are 6 debug registers in the set.
- **Designations:** The registers are numbered DR0 through DR7; however, DR4 and DR5 are considered obsolete synonyms for DR6 and DR7.
- **Function:** They are used by the processor specifically for program debugging.
- **Access Mechanism:** The registers are accessed using variants of the MOV instruction.
- **Security Restriction:** Instructions accessing these registers can only be executed at privilege level zero (Ring 0).
- **Context:** They function as a facet of the operating system.
- **Aliases:** Alternate names include "X86 디버그 레지스터."

## FAQs
### Q: How many debug registers exist in the x86 architecture?
A: There are 6 x86 debug registers. They are identified as DR0 through DR7, though DR4 and DR5 are obsolete synonyms for DR6 and DR7.

### Q: What level of privilege is required to access x86 debug registers?
A: Accessing x86 debug registers requires privilege level zero. Variants of the MOV instruction used to read or write these registers cannot be executed by standard user-mode software.

### Q: What is the primary purpose of the x86 debug register?
A: The primary purpose is program debugging. These registers serve as immediately accessible working storage for the digital processor to manage debugging tasks.

## Why It Matters
The x86 debug register set is a critical component in the architecture of modern computing, serving as the fundamental hardware interface for software debugging and system monitoring. By providing dedicated registers (DR0–DR7) within the processor itself, the architecture allows operating systems and debuggers to halt execution or monitor specific memory accesses without modifying the code being executed.

The strict access control—limiting MOV operations to privilege level zero—is vital for system stability and security. It ensures that user-level applications cannot tamper with debugging settings or crash the system by misconfiguring hardware breakpoints. This separation allows developers to diagnose complex issues in a controlled environment while maintaining the integrity of the operating system kernel. As a subclass of processor registers, they represent the specialized evolution of CPU design to support the rigorous demands of software development and operating system management.

## Notable For
- Being a specialized subclass of **processor register** dedicated to debugging.
- The specific numbering scheme (DR0–DR7) where two registers (DR4, DR5) are **obsolete synonyms** for others.
- Requiring **privilege level zero** for access, distinguishing them from general-purpose registers available to user applications.
- Functionality that is deeply integrated as a **facet of the operating system**.

## Body
### Definition and Classification
The x86 debug register is a class of processor register found within the x86 architecture. As immediately accessible working storage available as part of a digital processor, these registers are distinct from general-purpose registers due to their specific role in hardware debugging. They are classified as a subclass of the standard processor register.

### Register Layout and Quantity
The architecture defines a set of 6 debug registers. These are addressed numerically:
- **DR0 through DR3:** Used for debugging.
- **DR4 and DR5:** These are understood as obsolete synonyms for DR6 and DR7 respectively.
- **DR6 and DR7:** Control and status registers (encompassing the obsolete synonyms).

This numbering system (DR0...DR7) covers the full range of available hardware debugging slots.

### Access and Privilege
Interaction with the x86 debug registers is highly restricted compared to other registers.
- **Instruction Set:** They are accessed exclusively via variants of the `MOV` instruction.
- **Privilege Level:** These specific instructions are privileged. They can only be executed at **privilege level zero** (often referred to as Ring 0). This restriction ensures that only the operating system kernel or highly privileged debuggers can configure hardware breakpoints, preventing standard applications from interfering with low-level processor operations.