# Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models

> Research article (2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021) · cited 10× · AI/ML

**Wikidata**: [openalex:W3210162968](https://www.wikidata.org/wiki/openalex:W3210162968)  
**Source**: https://4ort.xyz/entity/towards-fault-simulation-at-mixed-register-transfer-gate-level-models