# Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs

> Research article (2018 IEEE International Conference on Networking, Architecture and Storage (NAS), 2018) · cited 57× · AI/ML

**Wikidata**: [openalex:W2898655385](https://www.wikidata.org/wiki/openalex:W2898655385)  
**Source**: https://4ort.xyz/entity/tolerating-soft-errors-in-deep-learning-accelerators-with-reliable-on-chip-memory-designs