# three-state logic

> Buffer in digital electronics

**Wikidata**: [Q1929956](https://www.wikidata.org/wiki/Q1929956)  
**Wikipedia**: [English](https://en.wikipedia.org/wiki/Three-state_logic)  
**Source**: https://4ort.xyz/entity/three-state-logic

## Summary
Three-state logic is a digital-electronics buffer design that adds a deliberate high-impedance (high-Z) state to the normal 0 and 1 logic levels, letting many devices share one wire without electrical conflict. By going electrically “invisible,” a three-state output lets a single bus be driven by whichever chip is currently enabled while the rest stay quiet.

## Key Facts
- Classified in Wikidata as an instance of “electronic component” with 15 Wikipedia language editions covering the topic.
- Also marketed and catalogued under the aliases “Tri-state,” “Tristate-Gatter,” “三态门,” “عازل ثلاثي الحالة,” and “Sortie à trois états.”
- Freebase identifier /m/06b1cd was last referenced 28 Oct 2013.
- Microsoft Academic (now discontinued) listed the concept under ID 150731610.
- Sitelink count across Wikimedia projects: 15 (as captured in the source).

## FAQs
### Q: What does the third state actually do?
A: Instead of driving the line high or low, the buffer enters a high-impedance mode that electrically disconnects its output, letting another device control the shared wire without contention.

### Q: Where are three-state buffers used?
A: They are found on processor buses, memory data lines, and any backplane where multiple ICs must take turns sending data over the same conductors.

### Q: Is three-state the same as open-collector/open-drain?
A: No. Open-collector schemes rely on an external pull-up resistor and wired-AND logic, whereas three-state drivers actively drive high, low, or float, giving faster switching and lower power on wide buses.

## Why It Matters
Before three-state logic, board-level buses needed either massive multiplexers or power-hungry resistor networks to keep outputs from fighting one another. The advent of the high-impedance third state meant designers could build backplanes with dozens of chips time-sharing the same copper, slashing pin count, cost, and power. It underpins every shared system bus from 1970s microcomputers to modern DDR memory, PCI-Express, and on-chip SoC fabrics. Without it, the proliferation of plug-in cards, memory modules, and multicore cache-coherent buses would have been far more complex and far less scalable.

## Notable For
- First commercial buffers to offer a high-Z mode, enabling “bus” architectures that became the backbone of microcomputer design.
- Universally catalogued part across vendors, making “tri-state” a genericized term for three-output buffers.
- Distinct from open-collector because it preserves active pull-up/pull-down drive in the enabled states, yielding faster edges and no static pull-up current.
- Supported by dedicated control pins (often OE, “output enable”), letting systems turn entire subsystems on and off electrically within nanoseconds.
- Found in every major hardware description language (VHDL, Verilog) as a standard logic value ‘Z’, showing its entrenched role in chip design.

## Body
### Functional Principle
A three-state buffer adds an enable input to an ordinary push-pull output stage. When enable is asserted, the part behaves as a conventional driver. When disabled, both pull-up and pull-down transistors switch off, presenting a near-infinite impedance to the line. The result is an effective disconnection, allowing another agent to drive without collision.

### Typical Packaging
Although the source material does not specify exact packages, industry practice places these buffers in everything from single-gate SOT-23 devices to 16-bit wide bus transceivers in 0.5-mm-pitch TQFPs. Control pins are usually shared per byte or nibble to minimize pin overhead.

### Integration Levels
Early boards used discrete three-state buffers; later they were absorbed into PALs, GALs, and CPLDs. Today the function lives inside every GPIO pin of a microcontroller as well as inside complex memory controllers, PCIe PHYs, and network switch crossbars.

### Design Implications
Because only one driver may be active at a time, protocol logic must guarantee mutually exclusive enables. Violating this rule causes bus contention, elevated current, and possible device damage. Modern systems add contention-detection circuits or timed dead cycles to prevent overlap.

## References

1. Freebase Data Dumps. 2013