# Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip

> Research article (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015) · cited 24× · AI/ML

**Wikidata**: [openalex:W2308963902](https://www.wikidata.org/wiki/openalex:W2308963902)  
**Source**: https://4ort.xyz/entity/thermal-analysis-and-interpolation-techniques-for-a-logic-wideio-stacked-dram-test-chip
