# Technology-design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip

> Research article (Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015) · cited 59× · AI/ML

**Wikidata**: [openalex:W4249616338](https://www.wikidata.org/wiki/openalex:W4249616338)  
**Source**: https://4ort.xyz/entity/technology-design-co-optimization-of-resistive-cross-point-array-for-accelerating-learning-algorithms-on-chip