# Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations

> Research article (MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021) · cited 18× · AI/ML

**Wikidata**: [openalex:W3205578621](https://www.wikidata.org/wiki/openalex:W3205578621)  
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