# Synchronous reference frame single‐phase phase‐locked loop (PLL) algorithm based on half‐cycle DFT

> Research article (IET Power Electronics, 2020) · cited 26× · AI/ML

**Wikidata**: [openalex:W3012807160](https://www.wikidata.org/wiki/openalex:W3012807160)  
**Source**: https://4ort.xyz/entity/synchronous-reference-frame-singlephase-phaselocked-loop-pll-algorithm-based-on-halfcycle-dft