# SweRV

> first open RISC-V processing core design and series of its descendants

**Wikidata**: [Q104152389](https://www.wikidata.org/wiki/Q104152389)  
**Source**: https://4ort.xyz/entity/swerv

## Summary
SweRV is a series of processing core designs based on the RISC-V instruction set architecture, developed by Western Digital. It is recognized as the first open RISC-V processing core design and is classified as open hardware, allowing its design documents to be openly accessed and modified by others.

## Key Facts
- **Developer:** Western Digital
- **Category:** Semiconductor intellectual property core; Open hardware
- **License:** Apache Software License 2.0
- **Programming Language:** SystemVerilog
- **Initial Publication Date:** January 24, 2019
- **Latest Recorded Version:** 1.9 (released February 3, 2021)
- **Source Code Repository:** https://github.com/chipsalliance/Cores-SweRV
- **Copyright Status:** Copyrighted

## FAQs
### Q: Who developed the SweRV core?
A: SweRV was developed by Western Digital. It serves as a semiconductor intellectual property core for their products and the broader open-source community.

### Q: Is SweRV considered open source?
A: Yes, SweRV is classified as "open hardware." Its design documents are openly accessible to and modifiable by others under the Apache Software License 2.0.

### Q: What hardware description language is used for SweRV?
A: The SweRV core is written in SystemVerilog, a standard hardware description and hardware verification language used in electronic design automation.

## Why It Matters
SweRV represents a significant shift in the semiconductor industry toward open hardware collaboration. As the first open RISC-V processing core design from a major storage corporation (Western Digital), it demonstrated that proprietary architectures could be replaced by customizable, open-standard alternatives without sacrificing performance or reliability. By releasing SweRV under the Apache Software License 2.0, Western Digital enabled developers and engineers to modify, optimize, and integrate the core into their own system-on-chip (SoC) designs freely. This move helps reduce development costs, accelerates time-to-market for new devices, and fosters a collaborative ecosystem around the RISC-V ISA, challenging the dominance of closed, proprietary architectures in the embedded and storage markets.

## Notable For
- **Industry First:** Identified as the first open RISC-V processing core design and series of its descendants.
- **Corporate Backing:** Developed by Western Digital, a major global data storage manufacturer, legitimizing the use of RISC-V in commercial products.
- **Open Accessibility:** Designated as open hardware, allowing for broad modification and accessibility unlike traditional closed IP cores.
- **Standardization:** Utilizes SystemVerilog, a widely accepted industry standard for hardware description.

## Body
### Development and Classification
SweRV is a semiconductor intellectual property core developed by Western Digital. It was initially published on January 24, 2019. The project is distinct in its classification as **open hardware**, defined as hardware whose design documents are openly accessible to and modifiable by others.

### Technical Specifications
The core is implemented using **SystemVerilog**, a hardware description and hardware verification language. While the design is open and modifiable, the entity retains a copyrighted status. The software license governing the design is the **Apache Software License 2.0**.

### Version History
Since its inception, the SweRV project (specifically the Cores-SweRV repository) has undergone multiple updates. Key releases include:
*   **Version 1.2:** Released January 22, 2021.
*   **Version 1.5:** Released January 22, 2021.
*   **Version 1.6:** Released January 22, 2021.
*   **Version 1.7:** Released January 22, 2021.
*   **Version 1.8:** Released January 22, 2021.
*   **Version 1.9:** Released February 3, 2021 (marked as a preferred version).

The source code for these versions is maintained at the GitHub repository hosted by the CHIPS Alliance.

## References

1. [Source](https://github.com/westerndigitalcorporation/swerv_eh1/commit/c5844e06f23004d7ae896be51e858b014d3ed041)
2. [Release 1.2. 2021](https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.2)
3. [Release 1.5. 2021](https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.5)
4. [Release 1.6. 2021](https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.6)
5. [Release 1.7. 2021](https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.7)
6. [Release 1.8. 2021](https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.8)
7. [Release 1.9. 2021](https://github.com/chipsalliance/Cores-SweRV/releases/tag/v1.9)