# Spacer Design Strategies at Sub-5-nm Technology Node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy—A Dielectric Perspective

> Research article (IEEE Transactions on Dielectrics and Electrical Insulation, 2024) · cited 10× · AI/ML

**Wikidata**: [openalex:W4404317259](https://www.wikidata.org/wiki/openalex:W4404317259)  
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