# Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays

> Research article (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023) · cited 32× · AI/ML

**Wikidata**: [openalex:W4320712936](https://www.wikidata.org/wiki/openalex:W4320712936)  
**Source**: https://4ort.xyz/entity/sense-model-hardware-codesign-for-accelerating-sparse-cnns-on-systolic-arrays