# RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning

> Research article (2021 58th ACM/IEEE Design Automation Conference (DAC), 2021) · cited 62× · AI/ML

**Wikidata**: [openalex:W3211934115](https://www.wikidata.org/wiki/openalex:W3211934115)  
**Source**: https://4ort.xyz/entity/rl-sizer-vlsi-gate-sizing-for-timing-optimization-using-deep-reinforcement-learning