# Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing

> Research article (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017) · cited 23× · AI/ML

**Wikidata**: [openalex:W2603623014](https://www.wikidata.org/wiki/openalex:W2603623014)  
**Source**: https://4ort.xyz/entity/parasitic-aware-common-centroid-binary-weighted-capacitor-layout-generation-integrating-placement-routing-and-unit-capac