# Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

> Research article (2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021) · cited 38× · AI/ML

**Wikidata**: [openalex:W3185898267](https://www.wikidata.org/wiki/openalex:W3185898267)  
**Source**: https://4ort.xyz/entity/parasitic-aware-analog-circuit-sizing-with-graph-neural-networks-and-bayesian-optimization