# Noise Margin Modeling for Zero-$V_{\text {GS}}$ Load TFT Circuits and Yield Estimation

> Research article (IEEE Transactions on Electron Devices, 2016) · cited 10× · AI/ML

**Wikidata**: [openalex:W2245518720](https://www.wikidata.org/wiki/openalex:W2245518720)  
**Source**: https://4ort.xyz/entity/noise-margin-modeling-for-zero-v-text-gs-load-tft-circuits-and-yield-estimation