# Noise Margin, Delay, and Power Model for Pseudo-CMOS TFT Logic Circuits

> Research article (IEEE Transactions on Electron Devices, 2017) · cited 12× · AI/ML

**Wikidata**: [openalex:W2619602080](https://www.wikidata.org/wiki/openalex:W2619602080)  
**Source**: https://4ort.xyz/entity/noise-margin-delay-and-power-model-for-pseudo-cmos-tft-logic-circuits