# Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface

> Research article (2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2021) · cited 13× · AI/ML

**Wikidata**: [openalex:W4200624891](https://www.wikidata.org/wiki/openalex:W4200624891)  
**Source**: https://4ort.xyz/entity/modeling-and-analysis-of-system-level-power-supply-noise-induced-jitter-psij-for-4-gbps-high-bandwidth-memory-hbm-i-o-in