# Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays

> Research article (2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019) · cited 26× · AI/ML

**Wikidata**: [openalex:W2972054167](https://www.wikidata.org/wiki/openalex:W2972054167)  
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