# Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

> Research article (Japanese Journal of Applied Physics, 2015) · cited 25× · AI/ML

**Wikidata**: [openalex:W2024856706](https://www.wikidata.org/wiki/openalex:W2024856706)  
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