# Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic

> Research article (2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021) · cited 10× · AI/ML

**Wikidata**: [openalex:W3196072617](https://www.wikidata.org/wiki/openalex:W3196072617)  
**Source**: https://4ort.xyz/entity/low-bitwidth-cnn-accelerator-on-fpga-using-winograd-and-block-floating-point-arithmetic
