# Jitter Minimization in Digital PLLs with Mid-Rise TDCs

> Research article (IEEE Transactions on Circuits and Systems I Regular Papers, 2019) · cited 22× · AI/ML

**Wikidata**: [openalex:W2996914186](https://www.wikidata.org/wiki/openalex:W2996914186)  
**Source**: https://4ort.xyz/entity/jitter-minimization-in-digital-plls-with-mid-rise-tdcs