# Hardware performance counter > registers that count hardware-related activities **Wikidata**: [Q2070684](https://www.wikidata.org/wiki/Q2070684) **Wikipedia**: [English](https://en.wikipedia.org/wiki/Hardware_performance_counter) **Source**: https://4ort.xyz/entity/hardware-performance-counter ## Summary A hardware performance counter is a specialized processor register designed to count hardware-related activities within a digital processor. Also known as a Performance Monitoring Counter (PMC) or Performance Monitor Unit (PMU), it functions as immediately accessible working storage used primarily for profiling and adjustment. These registers allow for the precise measurement of specific metrics, such as instructions per cycle. ## Key Facts - **Classification:** Hardware performance counters are a subclass of processor registers, which serve as immediately accessible working storage for digital processors. - **Primary Function:** They are used specifically for profiling system performance and making hardware or software adjustments. - **Common Abbreviations:** The technology is frequently referred to by the acronyms HPC (Hardware Performance Counter), PMC (Performance Monitoring Counter), and PMU (Performance Monitor Unit). - **Measured Metrics:** These registers are capable of measuring specific hardware activities, including instructions per cycle. - **Software Integration:** The `perf` utility is a noted user of hardware performance counters. - **Architectural References:** The technology is referenced in technical documentation for architectures such as Arm (specifically the Arm Cortex-A77 Core) and the Linux kernel (specifically `arch/arm64/kernel/perf_event.c`). ## FAQs ### Q: What is a hardware performance counter? A: A hardware performance counter is a type of processor register that records and counts specific hardware-related activities. It acts as a high-speed storage location used to monitor the internal operations of a processor. ### Q: What is the difference between HPC, PMC, and PMU? A: These are synonyms and acronyms referring to the same technology. HPC stands for Hardware Performance Counter, PMC stands for Performance Monitoring Counter, and PMU stands for Performance Monitor Unit. ### Q: What are hardware performance counters used for? A: They are primarily used for profiling software performance and adjusting system configurations. By measuring data such as instructions per cycle, they help developers optimize code and system efficiency. ### Q: What tool utilizes hardware performance counters? A: The `perf` tool is identified as a user of hardware performance counters, interacting with them to monitor system performance. ## Why It Matters Hardware performance counters are essential components in the field of computer architecture and software optimization. Because they exist as a subclass of processor registers—the most immediately accessible form of working storage—they can monitor internal processor events with minimal overhead. This capability is critical for developers and system architects who need to understand the precise efficiency of code execution. By providing data on metrics like instructions per cycle, these counters allow for detailed profiling that goes beyond simple timing. This data drives the adjustment of both hardware configurations and software algorithms, directly influencing the speed and efficiency of computing tasks. Their integration into major operating systems like Linux (via tools like `perf` and architecture-specific kernel trees) highlights their fundamental role in maintaining and improving digital system performance. ## Notable For - **Direct Hardware Access:** Unlike software-based metrics, these counters are built directly into the processor register architecture, providing immediate data on hardware activities. - **Standardization:** The concept is standardized across different architectures, evidenced by specific implementations in major platforms like the Linux kernel and Arm architecture. - **Granular Metric Tracking:** Specifically capable of tracking granular metrics such as "instructions per cycle." - **Role in Optimization:** They provide the raw data necessary for performance profiling and system adjustment. ## Body ### Technical Classification A hardware performance counter is technically classified as a **processor register**. It inherits the properties of being "immediately accessible working storage available as part of a digital processor." While general-purpose registers handle data for operations, hardware performance counters are specialized to accumulate counts of specific hardware events. ### Naming and Terminology The entity is known by several names and acronyms across the industry: * **Hardware Performance Counter (HPC)** * **Performance Monitoring Counter (PMC)** * **Performance Monitor Unit (PMU)** The term "Performance Monitor Unit" is specifically referenced in technical manuals for the **Arm Cortex-A77 Core** and associated Linux kernel driver code (`arch/arm64/kernel/perf_event.c`). ### Application and Usage The primary utility of hardware performance counters lies in **profiling** and **adjustment**. * **Profiling:** By counting events, developers can identify bottlenecks in code execution. * **Adjustment:** System parameters can be tuned based on the feedback provided by the counters. A specific metric associated with these counters is **instructions per cycle**, which measures the efficiency of a processor at the hardware level. The data provided by these registers is utilized by performance analysis tools such as **perf**. ## References 1. [Source](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/kernel/perf_event.c) 2. [Arm Cortex-A77 Core Technical Reference Manual r1p1](https://developer.arm.com/documentation/101111/0101/debug-descriptions/performance-monitor-unit)