# FPGA‐based active disturbance rejection velocity control for a parallel DC/DC buck converter‐DC motor system

> Research article (IET Power Electronics, 2019) · cited 28× · AI/ML

**Wikidata**: [openalex:W2989092696](https://www.wikidata.org/wiki/openalex:W2989092696)  
**Source**: https://4ort.xyz/entity/fpgabased-active-disturbance-rejection-velocity-control-for-a-parallel-dc-dc-buck-converterdc-motor-system