# FPGA Design of a Variable Step-Size Variable Tap Length Denlms Filter with Hybrid Systolic-Folding Structure and Compressor-Based Booth Multiplier for Noise Reduction in Ecg Signal

> Research article (Circuits Systems and Signal Processing, 2022) · cited 17× · AI/ML

**Wikidata**: [openalex:W4212796480](https://www.wikidata.org/wiki/openalex:W4212796480)  
**Source**: https://4ort.xyz/entity/fpga-design-of-a-variable-step-size-variable-tap-length-denlms-filter-with-hybrid-systolic-folding-structure-and-compres