# Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise

> Research article (IEEE Transactions on Circuits and Systems I Regular Papers, 2023) · cited 14× · AI/ML

**Wikidata**: [openalex:W4386131896](https://www.wikidata.org/wiki/openalex:W4386131896)  
**Source**: https://4ort.xyz/entity/enhanced-jitter-analysis-and-minimization-for-digital-plls-with-mid-rise-tdcs-and-its-impact-on-output-phase-noise