# Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

> Research article (IEEE Design and Test, 2019) · cited 17× · AI/ML

**Wikidata**: [openalex:W2981151545](https://www.wikidata.org/wiki/openalex:W2981151545)  
**Source**: https://4ort.xyz/entity/enabling-timing-error-resilience-for-low-power-systolic-array-based-deep-learning-accelerators