# Design of synchronous reference frame phase‐locked loop with the presence of dc offsets in the input voltage

> Research article (IET Power Electronics, 2015) · cited 47× · AI/ML

**Wikidata**: [openalex:W2296302142](https://www.wikidata.org/wiki/openalex:W2296302142)  
**Source**: https://4ort.xyz/entity/design-of-synchronous-reference-frame-phaselocked-loop-with-the-presence-of-dc-offsets-in-the-input-voltage