# Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

> Research article (IEEE Access, 2020) · cited 33× · AI/ML

**Wikidata**: [openalex:W2999934268](https://www.wikidata.org/wiki/openalex:W2999934268)  
**Source**: https://4ort.xyz/entity/design-of-a-high-performance-phase-locked-loop-with-dc-offset-rejection-capability-under-adverse-grid-condition