# core complex

> a logical component of AMD Zen CPU microarchitectures

**Wikidata**: [Q111442173](https://www.wikidata.org/wiki/Q111442173)  
**Source**: https://4ort.xyz/entity/core-complex

## Summary
A core complex (CCX) is AMD’s modular building block inside every Zen-family processor that groups four or eight CPU cores together with their shared cache and control logic. It is the smallest repeatable unit AMD combines to scale from laptop chips to 64-core server parts.

## Key Facts
- AMD created the core-complex concept for the 2017 Zen microarchitecture and has kept it through Zen 4.
- Each Zen, Zen+, and Zen 2 CCX contains exactly four physical CPU cores; Zen 3 doubled the count to eight cores per CCX.
- A single CCX also includes the associated L3 cache and the interconnect that lets the cores behave as one cache-coherent domain.
- The company packages one or more CCX dies (chiplets) inside the same processor package to build Ryzen, Threadripper, and EPYC products.
- Because the CCX is a logical grouping, its physical footprint is determined by the process node used for the core-complex die (CCD).

## FAQs
### Q: How many cores are in one CCX?
A: Four cores in Zen, Zen+, and Zen 2; eight cores in Zen 3 and later.

### Q: Is a CCX the same as a CCD?
A: No. The CCX is the logical group of cores; the CCD (core-complex die) is the silicon chiplet that can hold one or two CCXs.

### Q: Why did AMD enlarge the CCX from four to eight cores in Zen 3?
A: Doubling the cores inside one CCX removed the cross-CCX latency penalty and let all eight cores share one large 32 MB L3 cache, improving gaming and server performance.

### Q: Can a processor have more than one CCX?
A: Yes. Ryzen, Threadripper, and EPYC parts combine multiple CCXs (and CCDs) to reach core counts far above eight.

## Why It Matters
Before Zen, AMD’s monolithic designs forced the company to build an entirely new chip for every product tier, inflating cost and design time. The CCX modular approach lets AMD design once and reuse many times: the same four-core or eight-core CCX is replicated to create 6-core Ryzen 5s, 16-core Ryzen 9s, or 64-core EPYCs. This scalability slashes non-recurring engineering costs and gives AMD a single die that can serve laptops, desktops, and servers. Because each CCX is its own cache-coherent island, AMD can also disable defective cores within a CCX, boosting manufacturing yield and keeping consumer prices low. The CCX concept underpins AMD’s chiplet strategy, allowing the company to move the I/O to a separate, cheaper process node while the high-performance cores sit on an advanced node, a split that Intel’s monolithic designs still struggle to match. In short, the CCX is the key architectural decision that returned AMD to performance and market-share leadership after 2011-2016’s Bulldozer era.

## Notable For
- First x86 vendor to break a high-core-count CPU into uniform, reusable four-/eight-core islands (CCXs) instead of one large die.
- Zen 3’s eight-core CCX delivered the largest generational IPC jump (≈19 %) in AMD’s history by eliminating CCX-to-CCX latency.
- CCX modularity enables AMD to use identically-sized chiplets for everything from $99 Ryzen 3 to $7,000 EPYC, simplifying inventory and binning.

## Body
### Definition and Scope
A core complex is AMD’s term for the smallest logical cluster of CPU cores inside Zen microarchitectures. It contains the cores, their private L1/L2 caches, and the shared last-level cache (L3) that makes the cluster one cache-coherent domain.

### Evolution by Generation
- **Zen (2017)**: 4 cores, 8 MB L3 per CCX; two CCXs per 8-core die.
- **Zen+ (2018)**: same 4-core CCX, 12 nm shrink, minor latency tweaks.
- **Zen 2 (2019)**: still 4-core CCX, but now 16 MB L3 thanks to 7 nm density.
- **Zen 3 (2020)**: 8-core CCX with unified 32 MB L3, halving average latency.
- **Zen 4 (2022)**: retains 8-core CCX, moves to 5 nm and adds AVX-512 support.

### Physical Packaging
One or two CCXs are placed on a core-complex die (CCD). Desktop Ryzen uses one or two CCDs; EPYC uses up to eight CCDs, each holding two CCXs in Zen 2 or one CCX in Zen 3.