# Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

> Research article (2020 57th ACM/IEEE Design Automation Conference (DAC), 2020) · cited 24× · AI/ML

**Wikidata**: [openalex:W3092122249](https://www.wikidata.org/wiki/openalex:W3092122249)  
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