# Circuit-Level Technique to Design Variation- and Noise-Aware Reliable Dynamic Logic Gates

> Research article (IEEE Transactions on Device and Materials Reliability, 2018) · cited 15× · AI/ML

**Wikidata**: [openalex:W2789797762](https://www.wikidata.org/wiki/openalex:W2789797762)  
**Source**: https://4ort.xyz/entity/circuit-level-technique-to-design-variation-and-noise-aware-reliable-dynamic-logic-gates