# Capability Hardware Enhanced RISC Instructions

> computer architecture for security

**Wikidata**: [Q131873099](https://www.wikidata.org/wiki/Q131873099)  
**Wikipedia**: [English](https://en.wikipedia.org/wiki/Capability_Hardware_Enhanced_RISC_Instructions)  
**Source**: https://4ort.xyz/entity/capability-hardware-enhanced-risc-instructions

## Summary
Capability Hardware Enhanced RISC Instructions (CHERI) is a secure computer architecture that extends RISC-based systems with hardware-enforced capability-based security, developed to prevent common software vulnerabilities like buffer overflows and privilege escalation. It is designed for high-assurance computing environments and has been implemented in research projects such as CHERIBSD. CHERI integrates capability tokens directly into hardware, ensuring fine-grained access control and least-privilege execution.

## Key Facts
- **Aliases**: CHERI
- **Instance of**: Instruction set extension, computer architecture, computing terminology, capability-based addressing
- **Sitelink count**: 4
- **Wikipedia languages**: Catalan (ca), English (en), Persian (fa), Kara-Kalpak (kaa)
- **Wikidata description**: Computer architecture for security
- **Developed by**: Collaboration between the University of Cambridge, SRI International, and others
- **Primary platform**: Extends RISC-V and ARM architectures
- **Key feature**: Hardware-enforced capability-based security
- **Related standards**: Integrates with RISC-V, inspired by capability-based addressing
- **Notable implementations**: CHERIBSD (a hardened BSD operating system)
- **Research focus**: Mitigating memory safety vulnerabilities and enabling secure execution environments

## FAQs
### Q: What is CHERI, and how does it enhance security?  
A: CHERI is a hardware architecture that extends RISC systems with capability-based security, using hardware-enforced tokens to restrict memory access to explicitly authorized operations. This prevents attacks like buffer overflows by ensuring processes cannot access unauthorized memory regions.

### Q: How does CHERI differ from traditional security models?  
A: Unlike traditional address-based access control, CHERI uses unforgeable capability tokens validated by hardware, ensuring that access rights cannot be tampered with via software exploits. This provides stronger isolation and least-privilege enforcement compared to conventional operating system security mechanisms.

### Q: Where is CHERI currently used?  
A: CHERI is primarily used in research and high-security environments, such as the CHERIBSD operating system and experimental hardware projects. Its principles influence secure computing initiatives in academia, defense, and emerging technologies like IoT and cloud infrastructure.

### Q: What makes CHERI significant in computer architecture?  
A: CHERI demonstrates that capability-based security can be efficiently implemented in hardware, offering a scalable solution to modern cyber threats. Its open-source design and collaboration between academia and industry position it as a foundational model for next-generation secure processors.

## Why It Matters
CHERI represents a paradigm shift in secure computing by embedding capability-based security directly into hardware, addressing critical vulnerabilities in traditional architectures. It provides a practical framework for enforcing least-privilege access control, which is essential for mitigating attacks in complex, interconnected systems. By enabling hardware validation of capability tokens, CHERI ensures that security policies are enforced at the lowest level, reducing reliance on error-prone software mechanisms. Its influence extends to both academic research and industrial applications, particularly in domains requiring high assurance, such as military systems, critical infrastructure, and secure multi-tenant environments. CHERI’s integration with open standards like RISC-V also promotes interoperability and adoption, making it a cornerstone of efforts to build inherently secure computing platforms.

## Notable For
- **Hardware-enforced capability security**: Implements capability tokens as first-class hardware objects, validated by the CPU.
- **Least-privilege execution**: Ensures processes operate with minimal access rights, reducing attack surfaces.
- **Academic-industry collaboration**: Developed through partnerships between leading research institutions and technology organizations.
- **Open-source ecosystem**: Core designs and tools are openly available, fostering community-driven innovation.
- **Compatibility with RISC-V**: Extends the RISC-V instruction set, aligning with modern open-hardware initiatives.

## Body
### Overview
CHERI is a computer architecture designed to address inherent security flaws in conventional computing systems. It extends RISC-based processors with capability hardware, enabling fine-grained memory access control through unforgeable tokens. This approach directly mitigates vulnerabilities such as buffer overflows and use-after-free exploits, which plague traditional address-based security models.

### Technical Architecture
- **Capability Registers**: CHERI introduces dedicated hardware registers to store capability tokens, which specify memory regions and permitted operations (e.g., read, write, execute).
- **Hardware Validation**: The CPU validates capabilities during instruction execution, ensuring that access rights are enforced at the hardware level, independent of software policies.
- **Memory Safety**: By restricting pointer arithmetic and ensuring capabilities cannot be forged, CHERI prevents common memory corruption attacks without requiring additional software safeguards.

### Development & Collaboration
- **Key Contributors**: The University of Cambridge, SRI International, and the University of California, Berkeley, have driven CHERI’s development.
- **Funding & Support**: Research has been supported by organizations such as DARPA and the UK Engineering and Physical Sciences Research Council (EPSRC).
- **Open-Source Implementation**: CHERI’s designs and tools are publicly available, with active community engagement in projects like the CheriBSD operating system.

### Applications & Impact
- **High-Security Systems**: CHERI is used in experimental military and industrial control systems where compromise is unacceptable.
- **Research Platforms**: It serves as a testbed for novel security mechanisms, such as microsecond-granularity secure enclaves and compartmentalized execution environments.
- **Influence on Standards**: CHERI’s principles have informed ongoing efforts to integrate capability-based security into mainstream architectures like RISC-V and ARM.

### Related Technologies
- **Capability-Based Addressing**: CHERI operationalizes this security model in hardware, demonstrating its practicality in real-world systems.
- **RISC-V Integration**: By extending the RISC-V instruction set, CHERI aligns with the open-hardware movement, enabling secure, customizable processor designs.
- **CHERIBSD**: A hardened BSD variant that leverages CHERI capabilities to enforce strict process isolation and memory safety.

### Knowledge Representation
- **Multilingual Documentation**: CHERI is documented in Catalan, English, Persian, and Kara-Kalpak Wikipedia editions, reflecting its global research significance.
- **Structured Data Identifiers**: Referenced by Wikidata and academic databases, ensuring persistent linking across knowledge graphs.
- **Academic Recognition**: CHERI has been cited in over 100 peer-reviewed publications, establishing its credibility in the computer architecture and security communities.