# Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic

> Research article (Proceedings of the 54th Annual Design Automation Conference 2017, 2017) · cited 20× · AI/ML

**Wikidata**: [openalex:W2625940868](https://www.wikidata.org/wiki/openalex:W2625940868)  
**Source**: https://4ort.xyz/entity/boosting-the-performance-of-3d-charge-trap-nand-flash-with-asymmetric-feature-process-size-characteristic