# An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

> Research article (IEEE Transactions on Instrumentation and Measurement, 2017) · cited 44× · AI/ML

**Wikidata**: [openalex:W2770343006](https://www.wikidata.org/wiki/openalex:W2770343006)  
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