# An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

> Research article (IEEE Journal of Solid-State Circuits, 2020) · cited 16× · AI/ML

**Wikidata**: [openalex:W3083765802](https://www.wikidata.org/wiki/openalex:W3083765802)  
**Source**: https://4ort.xyz/entity/an-8-5-gb-s-pin-12-gb-lpddr5-sdram-with-a-hybrid-bank-architecture-low-power-and-speed-boosting-techniques