# An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz

> Research article (2017 Symposium on VLSI Circuits, 2017) · cited 24× · AI/ML

**Wikidata**: [openalex:W2743401663](https://www.wikidata.org/wiki/openalex:W2743401663)  
**Source**: https://4ort.xyz/entity/an-18-bit-2ms-s-pipelined-sar-adc-utilizing-a-sampling-distortion-cancellation-circuit-with-107db-thd-at-100khz