# An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3fs Jitter

> Research article (2024 IEEE Custom Integrated Circuits Conference (CICC), 2024) · cited 11× · AI/ML

**Wikidata**: [openalex:W4396918354](https://www.wikidata.org/wiki/openalex:W4396918354)  
**Source**: https://4ort.xyz/entity/an-11-1-to-14-9ghz-digital-integral-hybrid-proportional-fractional-n-pll-with-an-lc-dtc-achieving-0-52s-locking-time-and