# A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm<sup>2</sup>

> Research article (2019 Symposium on VLSI Circuits, 2019) · cited 12× · AI/ML

**Wikidata**: [openalex:W2965389440](https://www.wikidata.org/wiki/openalex:W2965389440)  
**Source**: https://4ort.xyz/entity/a-ternary-based-bit-scalable-8-80-tops-w-cnn-accelerator-with-many-core-processing-in-memory-architecture-with-896k-syna