# A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology

> Research article (2015 IEEE Custom Integrated Circuits Conference (CICC), 2015) · cited 11× · AI/ML

**Wikidata**: [openalex:W2180303965](https://www.wikidata.org/wiki/openalex:W2180303965)  
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