# A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures

> Research article (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015) · cited 53× · AI/ML

**Wikidata**: [openalex:W2292188910](https://www.wikidata.org/wiki/openalex:W2292188910)  
**Source**: https://4ort.xyz/entity/a-support-vector-regression-svr-based-latency-model-for-network-on-chip-noc-architectures