# A PVT-robust −59-dBc reference spur and 450-fs<inf>RMS</inf> jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop

> Research article (2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016) · cited 14× · AI/ML

**Wikidata**: [openalex:W2526637327](https://www.wikidata.org/wiki/openalex:W2526637327)  
**Source**: https://4ort.xyz/entity/a-pvt-robust-59-dbc-reference-spur-and-450-fs-lt-inf-gt-rms-lt-inf-gt-jitter-injection-locked-clock-multiplier-using-a-v