# A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design

> Research article (2017 47th European Solid-State Device Research Conference (ESSDERC), 2017) · cited 10× · AI/ML

**Wikidata**: [openalex:W2760897410](https://www.wikidata.org/wiki/openalex:W2760897410)  
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