# A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis

> Research article (Current Nanoscience, 2015) · cited 47× · AI/ML

**Wikidata**: [openalex:W2760788341](https://www.wikidata.org/wiki/openalex:W2760788341)  
**Source**: https://4ort.xyz/entity/a-model-to-improve-analysis-of-cntfet-logic-gates-in-verilog-a-part-i-static-analysis